module zad1 (CLOCK_50, HEX0, HEX1, HEX2, HEX3);

input CLOCK_50;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;

reg [4:0] steps = 5'd0;
reg [3:0] lol0 = 4'ha;
reg [3:0] lol1 = 4'ha;
reg [3:0] lol2 = 4'ha;
reg [3:0] lol3 = 4'ha;
wire clock;

clock_1s(CLOCK_50, clock);
hex_print(HEX0, lol3);
hex_print(HEX1, lol2);
hex_print(HEX2, lol1);
hex_print(HEX3, lol0);

always @(posedge clock)
begin
  steps <= steps + 1;
  case (steps)
    5'h0: begin
	   lol0 <= 4'ha;
		lol1 <= 4'ha;
		lol2 <= 4'ha;
		lol3 <= 4'h3;
	 end
    5'h1: begin
	   lol0 <= 4'ha;
		lol1 <= 4'ha;
		lol2 <= 4'h3;
		lol3 <= 4'h0;
	 end
    5'h2: begin
	   lol0 <= 4'ha;
		lol1 <= 4'h3;
		lol2 <= 4'h0;
		lol3 <= 4'h1;
	 end
    5'h3: begin
	   lol0 <= 4'h3;
		lol1 <= 4'h0;
		lol2 <= 4'h1;
		lol3 <= 4'h4;
	 end
    5'h4: begin
	   lol0 <= 4'h0;
		lol1 <= 4'h1;
		lol2 <= 4'h4;
		lol3 <= 4'h1;
	 end
    5'h5: begin
	   lol0 <= 4'h1;
		lol1 <= 4'h4;
		lol2 <= 4'h1;
		lol3 <= 4'h7;
	 end
    5'h6: begin
	   lol0 <= 4'h4;
		lol1 <= 4'h1;
		lol2 <= 4'h7;
		lol3 <= 4'ha;
	 end
    5'h7: begin
	   lol0 <= 4'h1;
		lol1 <= 4'h7;
		lol2 <= 4'ha;
		lol3 <= 4'ha;
	 end
    5'h8: begin
	   lol0 <= 4'h7;
		lol1 <= 4'ha;
		lol2 <= 4'ha;
		lol3 <= 4'ha;
	 end
    5'h9: begin
	   lol0 <= 4'ha;
		lol1 <= 4'ha;
		lol2 <= 4'ha;
		lol3 <= 4'ha;
	 end
	 default: begin
	   lol0 <= 4'ha;
		lol1 <= 4'ha;
		lol2 <= 4'ha;
		lol3 <= 4'ha;
	 end
  endcase
  if (steps == 9)
    steps <= 0;
end

endmodule

// 0..9		= 0..9
// a..e		=
// f			= L
module hex_print(output reg[6:0] o, input[3:0] i);
  always
  case (i) 
    4'h0 : o <= 7'b1000000;
	 4'h1 : o <= 7'b1111001;
	 4'h2 : o <= 7'b0100100;
	 4'h3 : o <= 7'b0110000;
	 4'h4 : o <= 7'b0011001;
	 4'h5 : o <= 7'b0010010;
	 4'h6 : o <= 7'b0000010;
	 4'h7 : o <= 7'b1111000;
	 4'h8 : o <= 7'b0000000;
	 4'h9 : o <= 7'b0010000;
	 4'hf : o <= 7'b1000111;
	 default: o <= 7'b1111111;
  endcase
endmodule

module clock_1s(input clk_in, output reg[0:0] clk_out);
  reg [26:0] counter = 26'd0;
  always @(posedge clk_in)
  begin
    counter <= counter + 1;
	 if (counter == 26'd50000000)
	 begin
	   clk_out <= ~clk_out;
		counter <= 0;
    end
  end
 endmodule